View DAC1005D650HWC15_1135168.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the dac1005d650 is a high-speed 10-bit dual-channel digital-to-analog converter (dac) with selectable 2 , 4 or 8 interpolating filters optimi zed for multi-carrier wireless transmitters. thanks to its digital on-chip modulation, the dac1005d650 allows the complex i and q inputs to be converted up from baseband (bb) to if. the mixing frequency is adjusted using a serial peripheral inte rface (spi) with a 32-bit nume rically controlled oscillator (nco). the phase is contro lled by a 16-bit register. two modes of operation are available: separate data ports or a single interleaved high-speed data port. in the interleaved mode, the input data stream is demultiplexed into its original i and q data and then latched. the dac1005d650 also includes a 2 , 4 and 8 clock multiplier which provides the appropriate internal clocks and an internal regulator to adjust the output full-scale current. 2. features and benefits dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating rev. 2 ? 3 september 2010 product data sheet ? dual 10-bit resolution ? imd3: 79 dbc; f s = 640 msps; f o =96mhz ? 650 msps maximum update rate ? sfdr: 75 dbc; f data =80mhz; f s = 640 msps; f o = 19 mhz; pll on ? selectable 2 , 4 or 8 interpolation filters ? typical 0.95 w power dissipation at 4 interpolation ? input data rate up to 160 msps ? power-down and sleep modes ? very low noise cap-free integrated pll ? differential scalable output current from 1.6 ma to 20 ma ? 32-bit programmable nco frequency ? on-chip 1.25 v reference ? dual-port or interleaved data modes ? external analog offset control (10-bit auxiliary dacs) ? 1.8 v and 3.3 v power supplies ? internal digital offset control ? lvds compatible clock ? inverse (sin x) / x function ? two?s complement or binary offset data format ? fully compatible spi port ? 3.3 v cmos input buffers ? industrial temperature range from ? 40 c to +85 c
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 2 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 3. applications ? wireless infrastructure: lte, wim ax, gsm, cdma, wcdma, td-scdma ? communication: lmds/mmds, point-to-point ? direct digital synthesis (dds) ? broadband wireless systems ? digital radio links ? instrumentation ? automated test equipment (ate) 4. ordering information table 1. ordering information type number package name description version dac1005d650hw/c1 htqfp100 plastic thermal enhanced thin quad flat package; 100 leads; body 14 14 1 mm; exposed die pad sot638-1
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 3 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 5. block diagram fig 1. block diagram 10 10 001aak158 dac1005d650 fir1 2 2 fir1 fir2 2 2 fir2 fir3 2 2 fir3 nco cos sin clock generator/ pll complex modulator latch q latch i clkp reset_n dac auxiliary dac auxiliary dac dac reference bandgap offset control 10-bit gain control 10-bit offset control 10-bit gain control 10-bit offset control sclk scs_n sdio sdo 62 66 8 41, 42 45 to 48, 51 to 54 18 to 25, 28, 29 9 63 65 64 2 3 90 91 68 69 86 85 74 73 clkn q0 to q9 dual port/ interleaved data modes i0 to i9 spi auxan gapout auxap ioutan vires ioutap ioutbn ioutbp auxbn auxbp mixer + ++ + a b + ? mixer mixer mixer x sin x x sin x
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 4 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 6. pinning information 6.1 pinning fig 2. pin configuration dac1005d650hw v dda(3v3) v dda(3v3) auxap auxbp auxan auxbn agnd agnd v dda(1v8) v dda(1v8) v dda(1v8) v dda(1v8) agnd gapout clkp vires clkn d.n.c. agnd reset_n v dda(1v8) scs_n d.n.c. sclk d.n.c. sdio tm1 sdo i7 n.c. i6 n.c. i5 q0 i4 q1 i3 tm0 v dd(io)(3v3) gndio i9 i8 q2 tm3 v dd(io)(3v3) gndio n.c. n.c. i2 q3 v ddd(1v8) agnd dgnd v dda(1v8) i1 agnd i0 v dda(1v8) n.c. agnd n.c. v dda(1v8) v ddd(1v8) agnd dgnd v dda(1v8) n.c. agnd n.c. ioutan v ddd(1v8) ioutap dgnd agnd tm2 n.c. dgnd agnd q7 v dda(1v8) q6 agnd q5 v dda(1v8) q4 agnd dgnd v ddd(1v8) q9/seliq q8 dgnd v ddd(1v8) v dda(1v8) ioutbp ioutbn agnd v dda(1v8) agnd v ddd(1v8) agnd 001aak159 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 56 55 54 53 52 51 15 16 17 18 19 61 60 59 58 57 26 27 28 29 30 31 32 33 34 35 36 37 38 39 45 46 47 48 49 50 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 81 80 79 78 77 76 40 41 42 43 44 86 85 84 83 82 agnd
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 5 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 6.2 pin description table 2. pin description symbol pin type [1] description v dda(3v3) 1 p analog supply voltage 3.3 v auxap 2 o auxiliary dac b output current auxan 3 o complementary auxiliary dac b output current agnd 4 g analog ground v dda(1v8) 5 p analog supply voltage 1.8 v v dda(1v8) 6 p analog supply voltage 1.8 v agnd 7 g analog ground clkp 8 i clock input clkn 9 i complement ary clock input agnd 10 g analog ground v dda(1v8) 11 p analog supply voltage 1.8 v d.n.c. 12 - do not connect d.n.c. 13 - do not connect tm1 14 i/o test mode 1 (to connect to dgnd) tm0 15 i/o test mode 0 (to connect to dgnd) v dd(io)(3v3) 16 p input/output buffers supply voltage 3.3 v gndio 17 g input/output buffers ground i9 18 i i data input bit 9 (msb) i8 19 i i data input bit 8 i7 20 i i data input bit 7 i6 21 i i data input bit 6 i5 22 i i data input bit 5 i4 23 i i data input bit 4 i3 24 i i data input bit 3 i2 25 i i data input bit 2 v ddd(1v8) 26 p digital supply voltage 1.8 v dgnd 27 g digital ground i1 28 i i data input bit 1 i0 29 i i data input bit 0 (lsb) n.c. 30 i not connected n.c. 31 i not connected v ddd(1v8) 32 p digital supply voltage 1.8 v dgnd 33 g digital ground n.c. 34 i not connected n.c. 35 i not connected v ddd(1v8) 36 p digital supply voltage 1.8 v dgnd 37 g digital ground tm2 38 - test mode 2 (to connect to dgnd) dgnd 39 g digital ground
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 6 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating v ddd(1v8) 40 p digital supply voltage 1.8 v q9/seliq 41 i q data input bit 9 (msb) select iq q8 42 i q data input bit 8 dgnd 43 g digital ground v ddd(1v8) 44 p digital supply voltage 1.8 v q7 45 i q data input bit 7 q6 46 i q data input bit 6 q5 47 i q data input bit 5 q4 48 i q data input bit 4 dgnd 49 g digital ground v ddd(1v8) 50 p digital supply voltage 1.8 v q3 51 i q data input bit 3 q2 52 i q data input bit 2 q1 53 i q data input bit 1 q0 54 i q data input bit 0 (lsb) n.c. 55 i not connected n.c. 56 i not connected n.c. 57 i not connected n.c. 58 i not connected gndio 59 g input/output buffers ground v dd(io)(3v3) 60 p input/output buffers supply voltage 3.3 v tm3 61 i/o test mode 3 (to connect to dgnd) sdo 62 o spi data output sdio 63 i/o spi data input/output sclk 64 i spi clock scs_n 65 i spi chip select (active low) reset_n 66 i general reset (active low) d.n.c. 67 - do not connect vires 68 i/o dac biasing resistor gapout 69 i/o bandgap input/output voltage v dda(1v8) 70 p analog supply voltage 1.8 v v dda(1v8) 71 p analog supply voltage 1.8 v agnd 72 g analog ground auxbn 73 o complementary auxiliary dac b output current auxbp 74 o auxiliary dac b output current v dda(3v3) 75 p analog supply voltage 3.3 v agnd 76 g analog ground v dda(1v8) 77 p analog supply voltage 1.8 v agnd 78 g analog ground v dda(1v8) 79 p analog supply voltage 1.8 v table 2. pin description ?continued symbol pin type [1] description
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 7 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating [1] p = power supply g = ground i = input o = output. [2] h = heatsink (exposed die pad to be soldered). agnd 80 g analog ground v dda(1v8) 81 p analog supply voltage 1.8 v agnd 82 g analog ground v dda(1v8) 83 p analog supply voltage 1.8 v agnd 84 g analog ground ioutbn 85 o complementary dac b output current ioutbp 86 o dac b output current agnd 87 g analog ground n.c. 88 - not connected agnd 89 g analog ground ioutap 90 o dac a output current ioutan 91 o complementary dac a output current agnd 92 g analog ground v dda(1v8) 93 p analog supply voltage 1.8 v agnd 94 g analog ground v dda(1v8) 95 p analog supply voltage 1.8 v agnd 96 g analog ground v dda(1v8) 97 p analog supply voltage 1.8 v agnd 98 g analog ground v dda(1v8) 99 p analog supply voltage 1.8 v agnd 100 g analog ground agnd h [2] g analog ground table 2. pin description ?continued symbol pin type [1] description
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 8 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 7. limiting values 8. thermal characteristics [1] in compliance with jedec test board, in free air. table 3. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd(io)(3v3) input/output supply voltage (3.3 v) ? 0.5 +4.6 v v dda(3v3) analog supply voltage (3.3 v) ? 0.5 +4.6 v v dda(1v8) analog supply voltage (1.8 v) ? 0.5 +3.0 v v ddd(1v8) digital supply voltage (1.8 v) ? 0.5 +3.0 v v i input voltage pins clkp, clkn, vires and gapout referenced to agnd ? 0.5 +3.0 v pins i9 to i0, q9 to q0, sdo, sdio, sclk, scs_n and reset_n re ferenced to gndio ? 0.5 +4.6 v v o output voltage pins ioutap, ioutan, ioutbp, ioutbn, auxap, auxan, auxbp and auxbn referenced to agnd ? 0.5 +4.6 v t stg storage temperature ? 55 +150 c t amb ambient temperature ? 45 +85 c t j junction temperature - 125 c table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient [1] 19.8 k/w r th(j-c) thermal resistance fr om junction to case [1] 7.7 k/w
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 9 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 9. characteristics table 5. characteristics v dda(1v8) = v ddd(1v8) = 1.8 v; v dda(3v3) = v dd(io)(3v3) = 3.3 v; agnd, dgnd and gndio short ed together; t amb = ? 40 cto+85 c; typical values measured at t amb = 25 c; r l = 50 ; i o(fs) = 20 ma; maximum sample rate; pll on; unless otherwise specified. symbol parameter conditions test [1] min typ max unit v dd(io)(3v3) input/output supply voltage (3.3 v) i3.03.33.6v v dda(3v3) analog supply voltage (3.3 v) i3.03.33.6v v dda(1v8) analog supply voltage (1.8 v) i1.71.81.9v v ddd(1v8) digital supply voltage (1.8 v) i1.71.81.9v i dd(io)(3v3) input/output supply current (3.3 v) f o = 19 mhz; f s = 640 msps; 8 interpolation; nco on i-513ma i dda(3v3) analog supply current (3.3 v) f o = 19 mhz; f s = 640 msps; 8 interpolation; nco on i-4826ma i ddd(1v8) digital supply current (1.8 v) f o = 19 mhz; f s = 640 msps; 8 interpolation; nco on i - 270 309 ma i dda(1v8) analog supply current (1.8 v) f o = 19 mhz; f s = 640 msps; 8 interpolation; nco on i - 330 358 ma i ddd digital supply current for x / (sin x) function only i - 67 - ma p tot total power dissipation f o = 19 mhz; f s = 320 msps; 4 interpolation; nco off; dac b off c - 0.53 - w f o = 19 mhz; f s = 320 msps; 4 interpolation; nco off c - 0.82 - w f o = 19 mhz; f s = 320 msps; 4 interpolation; nco on c - 0.94 - w f o = 19 mhz; f s = 640 msps; 8 interpolation; nco off c - 0.95 - w f o = 19 mhz; f s = 640 msps; 8 interpolation; nco on; all v dd i - 1.18 1.4 w f o = 19 mhz; f s = 640 msps; 8 interpolation; nco low power on c - 1.07 - w power-down mode full power-down; all v dd i - 0.08 0.13 w dac a and dac b sleep mode; 8 interpolation; nco on i - 0.88 - w
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 10 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating clock inputs (clkp and clkn) [2] v i input voltage clkp; or clkn | v gpd | <50mv c [3] 825 - 1575 mv v idth input differential threshold voltage | v gpd | < 50 mv c [3] ? 100 - +100 mv r i input resistance d - 10 - m c i input capacitance d - 0.5 - pf digital inputs (i0 to i13, q0 to q13) v il low-level input voltage c gndio - 1.0 v v ih high-level input voltage c2.3-v dd(io)(3v3) v i il low-level input current v il = 1.0 v i - 40 - a i ih high-level input current v ih = 2.3 v i - 80 - a digital inputs (sdo, sdio, sclk, scs_n and reset_n) v il low-level input voltage c gndio - 1.0 v v ih high-level input voltage c2.3-v dd(io)(3v3) v i il low-level input current v il = 1.0 v i - 20 - na i ih high-level input current v ih = 2.3 v i - 20 - na analog outputs (ioutap, ioutan, ioutbp and ioutbn) i o(fs) full-scale output current register value = 00h c - 1.6 - ma default register c - 20 - ma v o output voltage compliance range c 1.8 - v dda(3v3) v r o output resistance d - 250 - k c o output capacitance d - 3 - pf n dac(mono) dac monotonicity guaranteed d - 8 - bit e o offset error variation c - 6 - ppm/ c e g gain error variation c - 18 - ppm/ c reference voltage output (gapout) v o(ref) reference output voltage t amb = 25 ci1.21.251.29v v o(ref) reference output voltage variation c-117- ppm/ c i o(ref) reference output current external voltage 1.25 v d - 40 - a table 5. characteristics ?continued v dda(1v8) = v ddd(1v8) = 1.8 v; v dda(3v3) = v dd(io)(3v3) = 3.3 v; agnd, dgnd and gndio short ed together; t amb = ? 40 cto+85 c; typical values measured at t amb = 25 c; r l = 50 ; i o(fs) = 20 ma; maximum sample rate; pll on; unless otherwise specified. symbol parameter conditions test [1] min typ max unit
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 11 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating analog auxiliary outputs ( auxap, auxan, auxbp and auxbn) i o(aux) auxiliary output current differential outputs i - 2.2 - ma v o(aux) auxiliary output voltage compliance range c 0 - 2 v n dac(aux)mono auxiliary dac monotonicity guaranteed d - 10 - bit input timing (see figure 10 ) f data data rate dual-port mode input c - - 160 mhz t w(clk) clk pulse width c 1.5 - t data ? 1.5 ns t h(i) input hold time c 1.1 - - ns t su(i) input set-up time c 1.1 - - ns output timing f s sampling frequency c - - 650 msps t s settling time to 0.5 lsb d - 20 - ns nco frequency range; f s = 640 msps f nco nco frequency register value = 00000000h d - 0 - mhz register value = ffffffffh d - 640 - mhz f step step frequency d - 0.149 - hz low-power nco frequency range; f dac = 640 mhz f nco nco frequency register value = 00000000h d - 0 - mhz register value = f8000000h d - 620 - mhz f step step frequency d - 20 - mhz dynamic performance; pll on sfdr spurious-free dynamic range f data = 80 mhz; f s = 320 msps; b=f data / 2 f o = 35 mhz at 0 dbfs c - 82 - dbc f data = 80 mhz; f s = 640 msps; b=f data / 2 f o = 4 mhz at 0 dbfs i - 76 - dbc f o = 19 mhz at 0 dbfs i - 75 - dbc f data = 160 mhz; f s = 640 msps; b=f data / 2 f o = 70 mhz at 0 dbfs c - 82 - dbc table 5. characteristics ?continued v dda(1v8) = v ddd(1v8) = 1.8 v; v dda(3v3) = v dd(io)(3v3) = 3.3 v; agnd, dgnd and gndio short ed together; t amb = ? 40 cto+85 c; typical values measured at t amb = 25 c; r l = 50 ; i o(fs) = 20 ma; maximum sample rate; pll on; unless otherwise specified. symbol parameter conditions test [1] min typ max unit
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 12 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating [1] d = guaranteed by design; c = guaranteed by c haracterization; i = 100 % industrially tested. [2] clkp and clkn inputs are at differential lvds levels. an external differential resistor with a value of between 80 and 120 should be connected across the pins (see figure 8 ). [3] | v gpd | represents the ground potential difference voltage. this is the voltage that results from current flowing through the finite r esistance and the inductance between the receiver and the driver circuit ground. [4] imd3 rejection with ? 6 dbfs/tone. sfdr rbw restricted bandwidth spurious-free dynamic range f s = 640 msps; f o = 96 mhz at 0dbfs 2.51 mhz f offset 2.71 mhz; b = 30 khz i- ? 89 ? 83 dbc 2.71 mhz f offset 3.51 mhz; b = 30 khz i- ? 88 - dbc 3.51 mhz f offset 4 mhz; b = 30 khz i- ? 89 ? 81 dbc 4 mhz f offset 40 mhz; b=1mhz i- ? 83 ? 67 dbc imd3 third-order intermodulation distortion f s = 320 msps; 4 interpolation f o1 =49mhz; f o2 =51mhz c [4] -81- dbc f o1 =95mhz; f o2 =97mhz c [4] -80- dbc f s =640msps; 8 interpolation f o1 =95mhz; f o2 =97mhz i [4] 67 79 - dbc f o1 = 152 mhz; f o2 =154mhz c [4] -77- dbc acpr adjacent channel power ratio f data =76.8mhz; f s =614.4 msps; f o =96mhz 1 carrier; b = 5 mhz i - 64 - db 2 carriers; b = 10 mhz c - 61 - db 4 carriers; b = 20 mhz c - 60 - db f data = 153.6 mhz; f s = 614.4 msps; f o = 115.2 mhz 1 carrier; b = 5 mhz c - 67 - db 2 carriers; b = 10 mhz c - 63 - db 4 carriers; b = 20 mhz c - 60 - db f data = 153.6 mhz; f s = 614.4 msps; f o = 153.6 mhz 1 carrier; b = 5 mhz c - 65 - db 2 carriers; b = 10 mhz c - 63 - db 4 carriers; b = 20 mhz c - 60 - db nsd noise spectral density f s = 640 msps; 8 interpolation; f o = 19 mhz at 0 dbfs noise shaper disabled c - ? 138 - dbm/hz noise shaper enabled c - ? 139 - dbm/hz table 5. characteristics ?continued v dda(1v8) = v ddd(1v8) = 1.8 v; v dda(3v3) = v dd(io)(3v3) = 3.3 v; agnd, dgnd and gndio short ed together; t amb = ? 40 cto+85 c; typical values measured at t amb = 25 c; r l = 50 ; i o(fs) = 20 ma; maximum sample rate; pll on; unless otherwise specified. symbol parameter conditions test [1] min typ max unit
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 13 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 10. application information 10.1 general description the dac1005d650 is a dual 10-bit dac operat ing at up to 650 msps. each dac consists of a segmented architecture, comprising a 6-bit thermometer sub-dac and an 4-bit binary weighted sub-dac. with an input data rate of up to 160 mhz, and a maximum output sampling rate of 650 msps, the dac1005d650 allo ws more flexibility for wide bandwidth and multi-carrier systems. combined with its quadrature modulator and its 32-bit nco, the dac1005d650 simplifies the frequency selection of the syst em. this is also possible because of the 2 , 4 and 8 interpolation filters that remove undesired images. two modes are available for the digital input. in the dual-port mode, each dac uses its own data input line. in interleaved mode, both dacs use the same data input line. each dac generates two complementary current outputs on pins ioutap/ioutan and ioutbp/ioutbn. this provides a full-scale output current (i o(fs) ) up to 20 ma. an internal reference is available for the reference current which is externally adjustable using pin vires. there are embedd ed features which provide analog of fset correction (internal auxiliary dacs), digital offset control and gain adjust ment. all the functions can be set using a spi. the dac1005d650 operates at both 3.3 v an d 1.8 v using separate digital and analog power supplies. the digital inpu t is 3.3 v compliant and the cl ock input is lvds compliant. 10.2 serial interface (spi) 10.2.1 protocol description the dac1005d650 serial interface is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. it provides access to the registers that define the operating modes of the chip in both write and read modes. this interface can be configured as a 3-wire ty pe (sdio as bidirectional pin) or a 4-wire type (sdio and sdo as unidirectional pin, in put and output port respectively). in both configurations, sclk acts as the serial clock, and scs_n acts as the serial chip select bar. each read/write operation is sequenced by the scs_n signal and enabled by a low assertion to drive the chip with between 2 to 5 bytes, depending on the content of the instruction byte (see ta b l e 7 ).
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 14 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating in table 7 n1 and n0 indicate the number of bytes transferred after the instruction byte. a0 to a4 indicates which register is being ad dressed. in the case of a multiple transfer, this address concerns the firs t register after which the next registers follow directly in decreasing order according to table 9 ? register allocation map ? . 10.2.2 spi timing description spi can operate at a frequency of up to 15 mhz. the spi timing is shown in figure 4 . r/w indicates the mode access (see ta b l e 6 ). fig 3. spi protocol 001aaj81 2 reset_n scs_n sclk sdio sdo (optional) r/w n1 n0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 table 6. read or write mode access description r/w description 0 write mode operation 1 read mode operation table 7. number of bytes to be transferred n1 n0 number of bytes 0 0 1 byte transferred 0 1 2 bytes transferred 1 0 3 bytes transferred 1 1 4 bytes transferred fig 4. spi timing diagram 001aaj8 13 50 % t w(reset_n) t su(scs_n) t su(sdio) t h(sdio) t h(scs_n) t w(sclk) 50 % reset_n scs_n sclk sdio 50 % 50 %
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 15 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating the spi timing characteristics are given in ta b l e 8 . 10.2.3 detailed descriptions of registers an overview of the details for all registers is provided in table 9 . table 8. spi timing characteristics symbol parameter min typ max unit f sclk sclk frequency - - 15 mhz t w(sclk) sclk pulse width 30 - - ns t su(scs_n) scs_n set-up time 20 - - ns t h(scs_n) scs_n hold time 20 - - ns t su(sdio) sdio set-up time 10 - - ns t h(sdio) sdio hold time 5 - - ns t w(reset_n) reset_n pulse width 30 - - ns
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 16 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating table 9. register allocation map address register name r/w bit definition default b7 b6 b5 b4 b3 b2 b1 b0 bin hex dec 0 00h common r/w 3w_spi spi_rst clk_sel - mode_ sel coding ic_pd gap_pd 10000000 80 128 1 01h txcfg r/w nco_on nco_lp_ sel inv_sin_ sel modulation[2:0] interpol ation[1:0] 10000111 87 135 2 02h pllcfg r/w pll_pd - pll_div_ pd pll_div[1:0] pll_phase[1:0] pll_pol 00010000 10 16 3 03h freqnco_lsb r/w freq_nco[7:0] 01100110 66 102 4 04h freqnco_lisb r/w freq_nco[15:8] 01100110 66 102 5 05h freqnco_uisb r/w freq_nco[23:16] 01100110 66 102 6 06h freqnco_msb r/w freq_nco[31:24] 00100110 26 38 7 07h phinco_lsb r/w ph_nco[7:0] 00000000 00 0 8 08h phinco_msb r/w ph_nco[15:8] 00000000 00 0 9 09h dac_a_cfg_1 r/w dac_a_pd dac_a_ sleep dac_a_offset[2:0] - - - 00000000 00 0 10 0ah dac_a_cfg_2 r/w dac_a_gain_ coarse[1:0] dac_a_gain_fine[5:0] 01000000 40 64 11 0bh dac_a_cfg_3 r/w dac_a_gain_ coarse[3:2] dac_a_offset[8:3] 11000000 c0 192 12 0ch dac_b_cfg_1 r/w dac_b_pd dac_b_ sleep dac_b_offset[2:0] - - - 00000000 00 0 13 0dh dac_b_cfg_2 r/w dac_b_gain_ coarse[1:0] dac_b_gain_fine[5:0] 01000000 40 64 14 0eh dac_b_cfg_3 r/w dac_b_gain_ coarse[3:2] dac_b_offset[8:3] 11000000 c0 192 15 0fh dac_cfg r/w - - - - - - minus_ 3db noise_ shper 00000000 00 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 26 1ah dac_a_aux_msb r/w aux_a[9:2] 10000000 80 128 27 1bh dac_a_aux_lsb r/w aux_a_pd - - - - - aux_a[1:0] 00000000 00 0 28 1ch dac_b_aux_msb r/w aux_b[9:2] 10000000 80 128 29 1dh dac_b_aux_lsb r/w aux_b_pd - - - - - aux_b[1:0] 00000000 00 0
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 17 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 10.2.4 registers detailed description please refer to ta b l e 9 for a register overview and thei r default values. in the following tables, all default results are shown highlighted. table 10. common register (a ddress 00h) bit description default settings are shown highlighted. bit symbol access value description 7 3w_spi r/w serial interface bus type 0 4 wire spi 1 3 wire spi 6 spi_rst r/w serial interface reset 0no reset 1 performs a reset on all registers except 00h 5 clk_sel r/w data input latch 0 at clk rising edge 1 at clk falling edge 3 mode_sel r/w input data mode 0 dual-port 1 interleaved 2 coding r/w coding 0binary 1 two?s compliment 1 ic_pd r/w power-down 0disabled 1 all circuits (digital and analog, except spi) are switched off 0 gap_pd r/w internal bandgap power-down 0 power-down disabled 1 internal bandgap references are switched off table 11. txcfg register (address 01h) bit description default settings are shown highlighted. bit symbol access value description 7 nco_on r/w nco 0 disabled (the nco phase is reset to 0 ) 1 enabled 6 nco_lp_sel r/w low-power nco 0 disabled 1 nco frequency and phase given by the five msbs of the registers 06h and 08h respectively
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 18 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 4 to 2 modulation[2:0] r/w modulation 000 dual dac: no modulation 001 positive upper single sideband up-conversion 010 positive lower single sideband up-conversion 011 negative upper single sideband up-conversion 100 negative lower single sideband up-conversion 1 to 0 interpolation[1:0] r/w interpolation 01 f s = 2f clk 10 f s = 4f clk 11 f s = 8f clk table 12. pllcfg register (address 02h) bit description default settings are shown highlighted. bit symbol access value description 7 pll_pd r/w pll 0 switched on 1 switched off 5 pll_div_pd r/w pll divider 0 switched on 1 switched off 4 to 3 pll_div[1:0] r/w pll divider factor 00 f s =2 f clk 01 f s =4 f clk 10 fs = 8 fclk 2 to 1 pll_phase[1:0] r/w pll phase shift of f s 00 0 01 120 10 240 0 pll_pol r/w dac clock edge 0 normal 1 inverted table 13. freqnco_lsb register (address 03h) bit description bit symbol access value description 7 to 0 freq_nco[7:0] r/w - lower 8 bits for the nco frequency setting table 14. freqnco_lisb register (address 04h) bit description bit symbol access value description 7 to 0 freq_nco[15:8] r/w - lower intermediate 8 bits for the nco frequency setting table 11. txcfg register (address 01h) bit description ?continued default settings are shown highlighted. bit symbol access value description
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 19 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating table 15. freqnco_uisb register (address 05h) bit description bit symbol access value description 7 to 0 freq_nco[23:16] r/w - upper intermediate 8 bits for the nco frequency setting table 16. freqnco_msb register (address 06h) bit description bit symbol access value description 7 to 0 freq_nco[31:24] r/w - most signif icant 8 bits for the nco frequency setting table 17. phinco_lsb register (address 07h) bit description bit symbol access value description 7 to 0 ph_nco[7:0] r/w - lower 8 bits for the nco phase setting table 18. phinco_msb register (address 08h) bit description bit symbol access value description 7 to 0 ph_nco[15:8] r/w - most significant 8 bits for the nco phase setting table 19. dac_a_cfg_1 register (a ddress 09h) bit description default settings are shown highlighted. bit symbol access value description 7 dac_a_pd r/w dac a power 0on 1off 6 dac_a_sleep r/w dac a sleep mode 0disabled 1 enabled 5 to 3 dac_a_offset[2:0] r/w - lower 3 bits for the dac a offset table 20. dac_a_cfg_2 register (a ddress 0ah) bit description bit symbol access value description 7 to 6 dac_a_gain_coarse[1:0 ] r/w - least significant 2 bits for the dac a gain setting for coarse adjustment 5 to 0 dac_a_gain_fine[5:0] r/w - the 6 bi ts for the dac a fine adjustment gain setting table 21. dac_a_cfg_3 register (a ddress 0bh) bit description bit symbol access value description 7 to 6 dac_a_gain_coarse[3:2 ] r/w - most significant 2 bits for the dac a gain setting for coarse adjustment 5 to 0 dac_a_offset[8:3] r/w - most significant 6 bits for the dac a offset
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 20 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating table 22. dac_b_cfg_1 register (a ddress 0ch) bit description default settings are shown highlighted. bit symbol access value description 7 dac_b_pd r/w dac b power 0on 1off 6 dac_b_sleep r/w dac b sleep mode 0disabled 1 enabled 5 to 3 dac_b_offset[2:0] r/w lower 3 bits for the dac b offset table 23. dac_b_cfg_2 register (a ddress 0dh) bit description bit symbol access value description 7 to 6 dac_b_gain_coarse[1:0 ] r/w - less significant 2 bits for the dac b gain setting for coarse adjustment 5 to 0 dac_b_gain_fine[5:0] r/w - the 6 bits for the dac b gain setting for fine adjustment table 24. dac_b_cfg_3 register (address 0eh) bit description bit symbol access value description 7 to 6 dac_b_gain_coarse[3:2 ] r/w - most significant 2 bits for the dac b gain setting for coarse adjustment 5 to 0 dac_b_offset[8:3] r/w - most significant 6 bits for the dac b offset table 25. dac_cfg register (add ress 0fh) bit description default settings are shown highlighted. bit symbol access value description 1 minus_3db r/w nco gain 0unity 1 ? 3 db 0 noise_shper r/w noise shaper 0 disabled 1 enabled table 26. dac_a_aux_msb register (address 1ah) bit description bit symbol access value description 7 to 0 aux_a[9:2] r/w - most significant 8 bits for the auxiliary dac a table 27. dac_a_aux_lsb register (address 1bh) bit description default settings are shown highlighted. bit symbol access value description 7 aux_a_pd r/w auxiliary dac a power 0on 1off 1 to 0 aux_a[1:0] r/w lower 2 bits for the auxiliary dac a
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 21 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 10.3 input data the setting applied to mode_sel (register 00h[3]; see table 10 on page 17 ) defines whether the dac1005d650 operates in the dual-port mode or in the interleaved mode (see table 30 ). 10.3.1 dual-port mode the data input for dual-port mode operation is shown in figure 5 ? dual-port mode ? . each dac has its own independent data input. the data enters the input latch on the rising edge of the internal clock signal and is transferred to the dac latch. 10.3.2 interleaved mode the data input for interleaved mode operation is shown in figure 6 ? interleaved mode operation ? . table 28. dac_b_aux_msb register (address 1ch) bit description bit symbol access value description 7 to 0 aux_b[9:2] r/w - most significant 8 bits for the auxiliary dac b table 29. dac_b_aux_lsb register (address 1dh) bit description default settings are shown highlighted. bit symbol access value description 7 aux_b_pd r/w auxiliary dac b power 0on 1off 1 to 0 aux_b[1:0] r/w lower 2 bits for the auxiliary dac b table 30. mode selection bit 3 setting function i9 to i0 q9 to q0 0 dual-port mode (pin q9) active active 1 interleaved mode (pin seliq) active off n in qn = 0 to 9 and for in is 0 to 9. fig 5. dual-port mode 001aaj58 5 latch i 2 2 2 in fir 1 fir 1 fir 2 fir 2 fir 3 fir 3 latch q 2 2 2 qn
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 22 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating in the interleaved mode, both dacs use the sa me data input at twice the dual-port mode frequency. data enters the latch on the rising edge of the internal clock signal. the data is sent to either latc h i or latch q, see figure 6 ? interleaved mode operation ? and figure 7 ? interleaved mode timing (8x interpolation, latch on rising edge) ? . the seliq input (pin 41) allows the synchroniza tion of the internally de-multiplexed i and q channels. seliq can be either a synchronous or asynch ronous (single rising edge, single pulse) signal. the first data bits following the seliq rising edge are sent in channel i and the following data bits are sent in channel q. af ter this, the data is distributed alternately between both channels. 10.4 input clock the dac1005d650 can operate with a clock frequency of 160 mhz in the dual-port mode and up to 320 mhz in the interleaved mode. the input clock is lvds (see figure 8 ) but it can also be interfaced with cml (see figure 9 ). n in qn = 9 and for in is 0 to 9. fig 6. interleaved mode operation fig 7. interleaved mode timing (8x in terpolation, latch on rising edge) 001aaj58 6 latch i 2 2 2 fir 1 fir 1 fir 2 fir 2 fir 3 fir 3 latch q 2 2 2 in qn/seliq 001aaj81 4 n in seliq (synchronous alternative) seliq (asynchronous alternative 1) seliq (asynchronous alternative 2) clk dig latch i output latch q output xx n n + 2 n + 1 n + 2 n + 3 n + 4 n + 5 xx n + 1 n + 3
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 23 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 10.5 timing the dac1005d650 can operate at an update rate (f s ) of up to 650 msps and with an input data rate (f data ) of up to 160 mhz. the input timing is shown in figure 10 ? input timing diagram ? . the typical performances are measured at 50 % duty cycle but any timing within the limits of the characteristics will not alter the performance. in table 31 ? frequencies ? , the links between internal and external clocking are defined. the setting applied to pll_div[1:0] (register 02h[4:3]; see table 12 ? pllcfg register (address 02h) bit description ? ) allows the frequency between the digital part and the dac core to be adjusted. fig 8. lvds clock configuration fig 9. interfacing cml to lvds 001aah02 1 100 lvds clkp clkn lvds z diff = 100 001aah02 0 55 55 1.1 k 2.2 k 100 nf l 100 nf 100 nf clkp lvds clkn agnd v dda(1v8) 100 z diff = 100 n in qn = 0 to 9 and for in is 0 to 9. fig 10. input timing diagram 001aaj81 5 n t su(i) 90 % 50 % 90 % in/qn clk (clkp-clkn) t h(i) t w(clk) n + 1 n + 2
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 24 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating the settings applied to pll_phase[1: 0] (register 02h[2:1]) and pll_pol (register 02h[0]), allows adjustment of the phase and polarity of the sampling clock. this occurs at the input of the dac core and depends mainly on the sampling frequency. some examples are given in table 32 ? sample clock phase and polarity examples ? . table 31. frequencies mode clk input (mhz) input data rate (mhz) interpolation update rate (msps) pll_div[1:0] dual-port 160 160 2 320 01 (/4) dual-port 160 160 4 640 01 (/4) dual-port 80 80 8 640 10 (/8) interleaved 320 320 2 320 00 (/2) interleaved 320 320 4 640 00 (/2) interleaved 160 160 8 640 01 (/4) table 32. sample clock phase and polarity examples mode input data rate (mhz) interpolation update rate (msps) pll_phase [1:0] pll_pol dual-port 80 2 160 01 1 dual-port 80 4 320 01 0 dual-port 80 8 640 01 1 interleaved 160 2 160 01 1 interleaved 160 4 320 01 0 interleaved 160 8 640 01 1
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 25 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 10.6 fir filters the dac1005d650 integrates three selectab le finite impulse response (fir) filters which enable the device to use interpolation rates of 2 , 4 or 8 . all three interpolation filters have a stop-b and attenuation of at least 80 dbc and a pass-band ripple of less than 0.0005 db. the coefficients of the interpolation filters are given in table 33 ? interpolation filter coefficients ? . [1] h(n) is the digital filter coefficient. table 33. interpolation filter coefficients first interpolation filter [1] second interpolation filter [1] third interpolation filter [1] lower upper value lower upper value lower upper value h(1) h(55) ? 4 h(1) h(23) ? 2 h(1) h(15) ? 39 h(2) h(54) 0 h(2) h(22) 0 h(2) h(14) 0 h(3) h(53) 13 h(3) h(21) 17 h(3) h(13) 273 h(4) h(52) 0 h(4) h(20) 0 h(4) h(12) 0 h(5) h(51) ? 34 h(5) h(19) ? 75 h(5) h(11) ? 1102 h(6) h(50) 0 h(6) h(18) 0 h(6) h(10) 0 h(7) h(49) 72 h(7) h(17) 238 h(7) h(9) 4964 h(8) h(48) 0 h(8) h(16) 0 h(8) - 8192 h(9) h(47) ? 138 h(9) h(15) ? 660 - - - h(10) h(46) 0 h(10) h(14) 0 - - - h(11) h(45) 245 h(11) h(13) 2530 - - - h(12) h(44) 0 h(12) - 4096 - - - h(13) h(43) ? 408------ h(14)h(42)0------ h(15) h(41) 650 - - - - - - h(16)h(40)0------ h(17) h(39) ? 1003------ h(18)h(38)0------ h(19) h(37) 1521 - - - - - - h(20)h(36)0------ h(21) h(35) ? 2315------ h(22)h(34)0------ h(23) h(33) 3671 - - - - - - h(24)h(32)0------ h(25) h(31) ? 6642------ h(26)h(30)0------ h(27) h(29) 20756 - - - - - - h(28) 32768------
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 26 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 10.7 quadrature modulator and nco the quadrature modulator allows the 10-bit i and q data to be mixed with the carrier signal generated by the numeri cally controlled oscillator (nco). the frequency of the nco is programmed over 32-bit and allows the sign of the sine component to be inverted in order to operate positive or negative, lower or upper single sideband up-conversion. 10.7.1 nco in 32-bit when using the nco, the frequency can be set by the four registers freqnco_lsb, freqnco_lisb, freqnco_uisb a nd freqnco_msb over 32 bits. the frequency for the nco in 32-bit is calculated as follows: (1) where m is the decimal representation of freq_nco[31:0]. the phase of the nco can be set from 0 to 360 by both registers phinco_lsb and phinco_msb over 16 bits. the default setting is f nco = 96 mhz when f s = 640 msps and the default phase is 0 . 10.7.2 low-power nco when using the low-power nco, the frequency can be set by the 5 msb of register freqnco_msb. the frequency for the low-power nco is calculated as follows: (2) where m is the decimal representation of freq_nco[31:27]. the phase of the low-power nco can be set by the 5 msb of the register phinco_msb. 10.7.3 minus 3 db during normal use, a full-scale pattern will al so be full scale at the output of the dac. nevertheless, when the i and q data are simultaneously close to full scale, some clipping can occur and the minus_3db function can be used to reduce gain by 3 db in the modulator. this is to keep a full-scale range at the output of the dac without added interferers. 10.8 x / (sin x) due to the roll-off effect of th e dac, a selectable fir filter is inserted to compensate for the (sin x) / x effect. this filter introduc es a dc loss of 3.4 db. the coefficients are represented in table 34 ? inversion filter coefficients ? . f nco mf s 2 32 -------------- = f nco mf s 2 5 -------------- =
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 27 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating [1] h(n) is the digital filter coefficient. 10.9 dac transfer function the full-scale output current for each dac is the sum of the two complementary current outputs: (3) the output current depends on the digital input data: (4) (5) the setting applied to coding (register 00h[2]; see table 9 ? register allocation map ? ) defines whether the dac1005d650 operates wit h a binary input or a two?s complement input. table 35 ? dac transfer function ? shows the output current as a function of the input data, when i o(fs) = 20 ma. 10.10 full-scale current 10.10.1 regulation the dac1005d650 reference circuitry integrates an internal bandgap reference voltage which delivers a 1.25 v reference to the gapout pin. it is recommended to decouple pin gapout using a 100 nf capacitor. table 34. inversion filter coefficients first interpolation filter [1] lower upper value h(1) h(9) 2 h(2) h(8) ? 4 h(3) h(7) 10 h(4) h(6) ? 35 h(5) - 401 table 35. dac transfer function data (decimal) i9/q9 to i0/q0 ioutp ioutn binary two?s complement 0 00 0000 0000 10 0000 0000 0 ma 20 ma ... ... ... ... ... 512 10 0000 0000 00 0000 0000 10 ma 10 ma ... ... ... ... ... 1023 11 1111 1111 01 1111 1111 20 ma 0 ma i ofs () i ioutp i ioutn + = i ioutp i ofs () data 1023 --------------- - ?? ?? = i ioutn i ofs () 1023 data ? 1023 --------------------------------- - ?? ?? =
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 28 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating the reference current is generated us ing an external resistor of 910 (1 %) connected to pin vires. a control amplifier sets the appropriate full-scale current (i o(fs) ) for both dacs (see figure 11 ? internal reference configuration ? ). this configuration is optimum for temper ature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor. the dac current can also be set by applying an external reference voltage to the non-inverting input pin gapout and disabling the internal bandgap reference voltage with gap_pd (register 00h[0]; see table 10 ? common register (address 00h) bit description ? ). 10.10.2 full-scale current adjustment the default full-scale current (i o(fs) ) is 20 ma. it can be further adjusted for each dac using spi. the adjustment range is between 1.6 ma to 22 ma 10 %. the settings applied to dac_a_gain _coarse[3:0] (register 0ah; see table 20 ? dac_a_cfg_2 register (address 0ah) bit description ? and register 0bh; see table 21 ? dac_a_cfg_3 register (address 0bh) bit description ? ) and to dac_b_gain coarse[3:0] (register 0dh; see table 23 ? dac_b_cfg_2 register (address 0dh) bit description ? and register 0eh; see table 24 ? dac_b_cfg_3 register (address 0eh) bit description ? ) define the coarse variation of the full-scale current (see table 36 ? i o(fs) coarse adjustment ? ). fig 11. internal reference configuration 001aaj81 6 ref. bandgap gapout vires dac current sources array agnd agnd 100 nf 909 (1 %) table 36. i o(fs) coarse adjustment default settings are shown highlighted. dac_gain_coarse[3:0] i o(fs) (ma) decimal binary 0 0000 1.6 1 0001 3.0 2 0010 4.4 3 0011 5.8 4 0100 7.2 5 0101 8.6 6011010.0 7011111.4
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 29 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating the settings applied to dac_a_ga in_fine[5:0] (register 0ah; see table 20 ? dac_a_cfg_2 register (address 0ah) bit description ? ) and to dac_b_gain_fine[5:0] (register 0dh; see table 23 ? dac_b_cfg_2 register (address 0dh) bit description ? ) define the fine variation of the full-scale current (see table 37 ? i o(fs) fine adjustment ? ). the coding of the fine gain adjustment is two?s complement. 10.11 digital offset adjustment when the dac1005d650 analog output is dc connected to the next stage, the digital offset correction can be used to adjust the co mmon mode level at the output of the dac. it adds an offset at the end of the digital part, just before the dac. the settings applied to dac_a_offset[8:0] (register 09h; see table 19 ? dac_a_cfg_1 register (address 09h) bit description ? and register 0bh; see table 21 ? dac_a_cfg_3 register (address 0bh) bit description ? ) and to ?dac_b_offset[8:0]? (register 0ch; see table 22 ? dac_b_cfg_1 register (address 0ch) bit description ? and register 0eh; see table 24 ? dac_b_cfg_3 register (address 0eh) bit description ? ) define the range of variation of the digital offset (see table 38 ? digital offset adjustment ? ). 8 1000 12.8 9 1001 14.2 10 1010 15.6 11 1011 17.0 12 1100 18.5 13 1101 20.0 14 1110 21.0 15 1111 22.0 table 37. i o(fs) fine adjustment default settings are shown highlighted. dac_gain_fine[5:0] delta i o(fs) decimal two?s complement ? 32 10 0000 ? 10 % ... ... ... 0 00 0000 0 ... ... ... +31 01 1111 +10 % table 36. i o(fs) coarse adjustment ?continued default settings are shown highlighted. dac_gain_coarse[3:0] i o(fs) (ma) decimal binary
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 30 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 10.12 analog output the dac1005d650 has two output channels each of which produces two complementary current outputs. these allow the even-order harmonics and noise to be reduced. the pins are ioutap/ioutan and ioutbp/ioutbn respec tively and need to be connected using a load resistor r l to the 3.3 v analog power supply (v dda(3v3) ). refer to figure 12 for the equivalent analog output circui t of one dac. this circuit consists of a parallel combination of nmos current so urces, and their associated switches, for each segment. the cascode source configuration increases the output impedance of the source, thus improving the dynamic performance of t he dac by introducing less distortion. the device can provide an output level of up to 2 v o(p-p) depending on the application, the following stages and the targeted performances. table 38. digital offset adjustment default settings are shown highlighted. dac_offset[8:0] offset applied decimal two?s complement ? 256 1 0000 0000 ? 256 ? 255 1 0000 0001 ? 255 ... ... ... ? 1 1 1111 1111 ? 1 0 0 0000 0000 0 +1 0 0000 0001 +1 ... ... ... +254 0 1111 1110 +254 +255 0 1111 1111 +255 fig 12. equivalen t analog output circuit (one dac) 001aah01 9 v dda(3v3) agnd ioutap/ioutbp ioutan/ioutbn r l r l agnd
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 31 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 10.13 auxiliary dacs the dac1005d650 in tegrates two auxiliary dacs that can be used to compensate for any offset between the dac and the next stage in the transmission path. both auxiliary dacs have a re solution of 10-bit and are cu rrent sources (r eferenced to ground). the settings applied to aux_a[9:0] and aux_b[9:0] define the offset data. (6) the output cu rrent depends on the auxiliary dac data: (7) (8) table 39 ? auxiliary dac transfer function ? shows the output current as a function of the auxiliary dac data. table 39. auxiliary dac transfer function default settings are shown highlighted. data aux_a[9:0] and aux_b[9:0] (binary) i auxp i auxn 0 00 0000 0000 0 ma 2.2 ma ... ... ... ... 512 10 0000 0000 1.1 ma 1.1 ma ... ... ... ... 1023 11 1111 1111 2.2 ma 0 ma i oaux () i auxp i auxn + = auxp i oaux () aux 9:0 [] 1023 ------------------------ - ?? ?? = auxn i oaux () (1023 a ? ux 9:0 []) 1023 --------------------------------------------- ?? ?? =
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 32 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 10.14 output c onfiguration 10.14.1 basic output configuration the use of a differentially-coupled transf ormer output provides optimum distortion performance (see figure 13 ? differential output wit h transformer; v o(dif)(p-p) = 1 v ? ). in addition, it helps to match the impedan ce and provides electrical isolation. the dac1005d650 can operate up to 2 v o(p-p) differential outputs. in this configuration, it is recommended to connect the center tap of the transformer to a 62 resistor connected to the 3.3 v analog power supply, in order to adjust the dc common mode to approximately 2.7 v (see figure 14 ? differential output with transformer; v o(dif)(p-p) = 2 v ? ). 10.14.2 dc interface to an aqm when the system operation requires to keep the dc component of the spectrum, the dac1005d650 can use a dc interface to conn ect to an analog quadrature modulator (aqm). in this case, the offset compensation for lo cancellation c an be made with the use of the digital offset control in the dac. figure 15 provides an example of a connecti on to an aqm with a 1.7 v common mode input level. fig 13. differential output with transformer; v o(dif)(p-p) = 1 v fig 14. differential output with transformer; v o(dif)(p-p) = 2 v 001aaj81 7 50 50 50 ioutnp/ioutnn; v o(cm) = 2.8 v; v o(dif)(p-p) = 1 v ioutnp ioutnn 0 ma to 20 ma 2:1 0 ma to 20 ma v dda(3v3) v dda(3v3) 001aaj81 8 50 100 100 ioutnp/ioutnn; v o(cm) = 2.7 v; v o(dif)(p-p) = 2 v ioutnp ioutnn 0 ma to 20 ma 4:1 0 ma to 20 ma v dda(3v3) 62 v dda(3v3) v dda(3v3)
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 33 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating figure 16 provides an example of a connection to an aqm with a 3.3 v i(cm) common mode input level. fig 15. an example of a dc interface to a 1.7 v aqm fig 16. an example of a dc interface to a 3.3 v aqm 001aaj54 1 51.1 51.1 442 442 v dda(3v3) ioutnp ioutnn 0 ma to 20 ma bbp (1) ioutnp/ioutnn; v o(cm) = 2.67 v; v o(dif)(p-p) = 1.98 v (2) bbp/bbn; v i(cm) = 1.7 v; v i(dif)(p-p) = 1.26 v bbn aqm (v i(cm) = 1.7 v) 768 768 (1) (2) 001aaj54 2 54.9 54.9 237 237 v dda(3v3) ioutnp ioutnn bbp bbn aqm (v i(cm) = 3.3 v) 750 750 5 v 1.27 k 1.27 k (1) ioutnp/ioutnn; v o(cm) = 2.75 v; v o(dif)(p-p) = 1.97 v (2) bbp/bbn; v i(cm) = 3.3 v; v i(dif)(p-p) = 1.5 v (1) (2)
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 34 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating the auxiliary dacs can be used to control the offset in a pr ecise range or with precise steps. figure 17 provides an example of a dc interfac e with the auxiliary dacs to an aqm with a 1.7 v common mode input level. figure 18 provides an example of a dc interfac e with the auxiliary dacs to an aqm with a 3.3 v common mode input level. fig 17. an example of a dc interface to a 1.7 v i(cm) aqm using auxiliary dacs fig 18. an example of a dc interface to a 3.3 v i(cm) aqm using auxiliary dacs 001aaj54 3 51.1 51.1 442 442 v dda(3v3) ioutnp ioutnn 0 ma to 20 ma bbp bbn aqm (v i(cm) = 1.7 v) 698 698 51.1 51.1 auxnp auxnn 1.1 ma (typ.) (1) ioutnp/ioutnn; v o(cm) = 2.67 v; v o(dif)(p-p) = 1.94 v (2) bbp/bbn; v i(cm) = 1.7 v; v i(dif)(p-p) = 1.23 v; offset correction up to 36 mv (1) (2) 001aaj54 4 54.9 54.9 237 237 3.3 v ioutnp ioutnn auxnp auxnn bbp bbn aqm (v i(cm) = 3.3 v) 750 750 5 v 634 634 442 442 (1) ioutnp/ioutnn; v o(cm) = 2.75 v; v o(dif)(p-p) = 1.96 v (2) bbp/bbn; v i(cm) = 3.3 v; v i(dif)(p-p) = 1.5 v; offset correction up to 36 mv (1) (2)
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 35 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating the constraints to adjust the interface are the output compliance range of the dac and the auxiliary dacs, the input common mode le vel of the aqm, and the range of offset correction required. 10.14.3 ac interface to an aqm when the analog quadrature modulator (aqm) common mode voltage is close to ground, the dac1005d650 must be ac-coupled and th e auxiliary dacs are needed for offset correction. figure 18 provides an example of a connecti on to an aqm with a 0.5 v common mode input level when using auxiliary dacs. 10.15 power and grounding in order to obtain optimum performance, it is recommended that the 1.8 v analog power supplies on pins 5, 11, 71, 77 and 99 shoul d not be connected with th ose on pins 70, 79, 81, 83, 93, 95 and 97 on the top layer. to optimize the decoupling, the power supplies should be decoupled with the following pins: ? v ddd(1v8) : pin 26 with 27; pin 32 with 33; pin 36 with 37; pin 40 with 39; pin 44 with 43 and pin 50 with 49. ? v dd(io)(3v3) : pin 16 with 17 and pin 60 with 59. ? v dda(1v8) : pin 5 with 4; pin 6 with 7; pin 11 with 10; pin 71 with 72; pin 77 with 78; pins 79, 81, 83 with 80, 82, 84; pins 93, 95, 97 with 92, 94, 96 and pin 99 with 98. ? v dda(3v3) : pin 1 with 100 and pin 75 with 76. fig 19. an example of an ac interface to a 0.5 v i(cm) aqm using auxiliary dacs 001aaj589 66.5 66.5 10 nf v dda(3v3) ioutnp ioutnn 0 ma to 20 ma bbp bbn aqm (v i(cm) = 0.5 v) 2 k 2 k 5 v 174 174 34 34 auxnp auxnn 1.1 ma (typ.) 10 nf (1) ioutnp/ioutnn; v o(cm) = 2.65 v; v o(dif)(p-p) = 1.96 v (2) bbp/bbn; v i(cm) = 0.5 v; v i(dif)(p-p) = 1.96 v; offset correction up to 70 mv (1) (2)
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 36 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 10.16 alternative parts the following alternative parts are available. table 40. alternative parts type number description sampling frequency dac1205d650 dual 12-bit dac up to 650 msps dac1405d650 dual 14-bit dac up to 650 msps
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 37 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 11. package outline fig 20. package outline sot638-1 (htqfp100) unit a max. a 1 a 2 a 3 b p h d h e l p z d (1) z e (1) cely w v references outline version european projection issue date iec jedec jeita mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 1.15 0.85 7 0 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot638-1 ms-026 03-04-07 05-02-02 d (1) e (1) 14.1 13.9 16.15 15.85 d h e h 7.1 6.1 7.1 6.1 1.15 0.85 b p b p e e a 1 a l p detail x l (a 3 ) b 25 h d h e a 2 v m b d z d a c z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 10 mm scale htqfp100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad sot638- 1 d h e h exposed die pad side
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 38 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 12. abbreviations table 41. abbreviations acronym description bb baseband cdma code division multiple access cml current mode logic cmos complementary metal-oxide semiconductor dac digital-to-analog converter fir finite impulse response gsm global system for mobile communications if intermediate frequency imd3 third-order inter modulation distortion lisb lower intermediate significant byte lmds local multipoint distribution service lsb least significant bit lte long term evolution lvds low-voltage differential signaling mmds multichannel multipoint distribution service msb most significant bit nco numerically controlled oscillator nmos negative metal-oxide semiconductor pll phase-locked loop sfdr spurious-free dynamic range spi serial peripheral interface td-scdma time division-synchronous code division multiple access uisb upper intermediate significant byte wcdma wideband code division multiple access wimax worldwide interoperability for microwave access
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 39 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 13. glossary spurious-free dynamic range (sfdr): ? the ratio between the rms value of the reconstructed output sine wave and the rms value of the largest spurious observed (harmonic and non-harmonic, excluding dc component) in the frequency domain. intermodulation distortion (imd): ? from a dual-tone digital input sine wave (these two frequencies being close together), the intermodulation distortion products imd2 and imd3 (respectively, 2 nd and 3 rd order components) are defined below. imd2 ? the ratio of the rms value of either tone to the rms value of the worst 2 nd order intermodulation product. imd3 ? the ratio of the rms value of either tone to the rms value of the worst 3 rd order intermodulation product. restricted bandwidth spur ious-free dynamic range ? the ratio of the rms value of the reconstructed output sine wave to th e rms value of the noise, including the harmonics, in a given bandwidth centered around f offset . 14. revision history table 42. revision history document id release date data sheet status change notice supersedes dac1005d650 v2.0 20100903 product data sheet - dac1005d650 v1.0 modifications ? figure 18 corrected the value of the resistors on pin auxnp dac1005d650 v1.0 20090728 product data sheet - -
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 40 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
dac1005d650 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 2 ? 3 september 2010 41 of 42 nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors dac1005d650 dual 10-bit dac, up to 650 msps; 2 4 and 8 interpolating ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 3 september 2010 document identifier: dac1005d650 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 thermal characteristics . . . . . . . . . . . . . . . . . . 8 9 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 application information. . . . . . . . . . . . . . . . . . 13 10.1 general description . . . . . . . . . . . . . . . . . . . . 13 10.2 serial interface (spi) . . . . . . . . . . . . . . . . . . . 13 10.2.1 protocol description . . . . . . . . . . . . . . . . . . . . 13 10.2.2 spi timing description . . . . . . . . . . . . . . . . . . . 14 10.2.3 detailed descriptions of registers . . . . . . . . . . 15 10.2.4 registers detailed description. . . . . . . . . . . . . 17 10.3 input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.3.1 dual-port mode . . . . . . . . . . . . . . . . . . . . . . . . 21 10.3.2 interleaved mode . . . . . . . . . . . . . . . . . . . . . . 21 10.4 input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.6 fir filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.7 quadrature modulator and nco . . . . . . . . . . 26 10.7.1 nco in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.7.2 low-power nco . . . . . . . . . . . . . . . . . . . . . . . 26 10.7.3 minus 3 db . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.8 x / (sin x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.9 dac transfer function . . . . . . . . . . . . . . . . . . . 27 10.10 full-scale current . . . . . . . . . . . . . . . . . . . . . . 27 10.10.1 regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.10.2 full-scale current adjustment . . . . . . . . . . . . . 28 10.11 digital offset adjustment . . . . . . . . . . . . . . . . . 29 10.12 analog output . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.13 auxiliary dacs . . . . . . . . . . . . . . . . . . . . . . . . 31 10.14 output configuration . . . . . . . . . . . . . . . . . . . . 32 10.14.1 basic output configuration . . . . . . . . . . . . . . . 32 10.14.2 dc interface to an aqm . . . . . . . . . . . . . . . . . 32 10.14.3 ac interface to an aqm . . . . . . . . . . . . . . . . . 35 10.15 power and grounding . . . . . . . . . . . . . . . . . . . 35 10.16 alternative parts . . . . . . . . . . . . . . . . . . . . . . . 36 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 37 12 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 38 13 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 39 15 legal information . . . . . . . . . . . . . . . . . . . . . . 40 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 40 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 40 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 41 16 contact information . . . . . . . . . . . . . . . . . . . . 41 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

▲Up To Search▲

Price & Availability of DAC1005D650HWC15

	To Download DAC1005D650HWC15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .